Ventaglio: Sparse Tensor Contractions on Vector Processors for Transformer Inference

A recent research article presents Ventaglio, a configurable sparse execution unit that utilizes RISC-V Vector (RVV) ISA extensions, aimed at enhancing the efficiency of sparse tensor contractions during Transformer model inference on vector processors. This study tackles the performance limitations of current RVV architectures, which lack built-in support for indexed gather-accumulate-scatter operations, necessitating the use of software index decoding and L1-backed indexed memory operations. Ventaglio is incorporated into an open-source vector processing cluster and fabricated using 12nm FinFET technology, with the goal of optimizing sparse tensor contractions to achieve their maximum performance potential. The paper is available on arXiv under ID 2607.25504.