Simulation-Aware In-Context Policy Improvement for LLM-Aided Analog Layout Refinement

A recent preprint on arXiv (2608.13767) introduces a method for in-context policy enhancement that is aware of simulations, specifically for refining analog layouts with the help of large language models (LLMs). This research tackles the laborious iterative nature of analog integrated circuit (IC) layout design, which heavily depends on simulation-based refinements. Although end-to-end layout generators expedite initial placement and routing, they still necessitate manual adjustments of optimization parameters, often requiring numerous post-layout simulations to satisfy strict design criteria. While Bayesian Optimization (BO) is a standard approach for parameter tuning, it demands hundreds to thousands of evaluations, each involving expensive parasitic extraction and simulations, making it unfeasible at the layout stage. Although LLMs can enhance sample efficiency in tuning, their limited access to geometric context and design-specific heuristics hampers their effectiveness in layout optimization. The proposed approach seeks to boost LLM capabilities by integrating simulation feedback into the policy improvement process, which could decrease the number of simulations needed and enhance efficiency. This work, relevant to electronic design automation (EDA) and AI-assisted design, is authored by researchers and available on arXiv.