SCALE: Self-Supervised Framework for Local DRV Fixing at Advanced Semiconductor Nodes
SCALE, a novel framework, tackles the issue of fixing design-rule violations (DRV) in local place-and-route (P&R) at sub-2nm semiconductor nodes. As manufacturing technology progresses, traditional DRV fixing faces challenges due to intricate rule interactions, dense multi-layer routing geometries, and specific constraints from foundries. Although Large Language Models (LLMs) have demonstrated potential in EDA scripting and documentation, their use in understanding visual layouts remains largely uncharted, as identifying DRC violations from layout images necessitates accurate geometric reasoning and foundry-specific expertise not present in general-purpose VLM training. SCALE incorporates a self-supervised layout-generation phase, converting multi-layer layout geometry into structured text, enabling a fine-tuned language model to reconstruct randomly masked polygons based on surrounding BEOL context without violation labels. During inference, the model generates corrected layouts using natural language prompts. This framework is elaborated in a paper available on arXiv (2607.21850).
Key facts
- SCALE is a self-supervised constraint-aware layout generation framework for local P&R DRV fixing.
- It targets advanced semiconductor nodes below 2nm.
- Multi-layer layout geometry is serialized into structured text.
- A fine-tuned language model reconstructs masked polygons from BEOL context without violation labels.
- LLMs have shown capabilities in EDA scripting but not in visual layout understanding.
- Diagnosing DRC violations requires precise geometric reasoning and foundry-specific knowledge.
- The paper is available on arXiv with ID 2607.21850.
- The framework uses natural language prompts at inference for layout correction.
Entities
Institutions
- arXiv