Research demonstrates LLM technique reduces errors in hardware logic design automation

A novel method for using Large Language Models in hardware logic design automation significantly reduces hallucinations and omissions. The approach treats LLMs as lossless encoders and decoders for invertible problems, similar to lossless compression in information theory. Researchers applied this technique to transform Logic Condition Tables into Hardware Description Language code for a two-dimensional network-on-chip router. The system generated 1500-2000 lines of HDL code across 13 units using seven different LLM models. By reconstructing LCTs from the auto-generated HDL and comparing them to originals, the method confirms correct logic generation and detects errors. This process yields substantial productivity improvements for developers working on hardware design automation. The research was published on arXiv under identifier 2512.03053v2 with announcement type replace-cross.