Peking University's 3D chip design tool aids Huawei amid US sanctions
Researchers at Peking University have developed a prototype electronic design automation (EDA) tool compatible with Huawei's LogicFolding architecture, announced Monday. The tool, unveiled Tuesday by the School of Integrated Circuits, aims to support Huawei's semiconductor ambitions despite US-led export restrictions. Huawei's goal is to produce chips by 2031 matching 1.4-nanometre performance without Western tools. The company's new Tau Scaling Law strategy focuses on speeding electrical signals rather than shrinking transistors. Developing domestic EDA is a priority for Beijing as the market is dominated by Western firms Synopsys and Cadence Design Systems.
Key facts
- Peking University unveiled a prototype EDA tool on Tuesday.
- The tool is compatible with Huawei's LogicFolding architecture introduced on Monday.
- Huawei aims to produce chips by 2031 matching 1.4-nanometre performance.
- The global EDA market is dominated by Synopsys and Cadence Design Systems.
- Huawei's Tau Scaling Law focuses on speeding electrical signals instead of shrinking transistors.
- US export restrictions block China from buying advanced lithography machines.
- Developing domestic EDA is a top priority for Beijing.
- The tool was announced by the School of Integrated Circuits at Peking University.
Entities
Institutions
- Peking University
- Huawei Technologies
- School of Integrated Circuits
- Synopsys
- Cadence Design Systems
Locations
- Beijing
- China
- United States