NeuroAbs: A Neuro-Symbolic Framework for RTL Abstraction to Accelerate Hardware Property Checking
NeuroAbs is a newly introduced neuro-symbolic framework aimed at enhancing property checking within hardware formal verification. This process is crucial for validating the functional accuracy of hardware designs, yet demonstrating user-defined properties on intricate RTL designs poses significant difficulties. While abstraction techniques are typically employed to simplify system complexity, previous approaches often require extensive manual intervention or depend on rigid rule-based systems. NeuroAbs initiates the process with LLM-assisted RTL analysis to pinpoint signals ideal for abstraction. It subsequently merges LLM-driven abstraction with an AST-based symbolic RTL representation to ensure the generated abstraction aligns more closely with the desired transformation. Each abstraction's soundness is confirmed through satisfiability modulo theories (SMT). This research is detailed in arXiv paper 2608.17304v1, identified as a cross type.
Key facts
- NeuroAbs is a neuro-symbolic framework for RTL abstraction.
- It aims to accelerate property checking in hardware formal verification.
- It uses LLM-assisted RTL analysis to identify signals suitable for abstraction.
- It combines LLM-based abstraction with an AST-based symbolic RTL representation.
- The soundness of each abstraction is checked using satisfiability modulo theories (SMT).
- Prior RTL abstraction methods require significant manual effort or rely on rule-based techniques that lack flexibility.
- The paper is available on arXiv with identifier 2608.17304v1.
- The announcement type is cross.
Entities
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