LLM-Driven Design Space Exploration for FPGA Accelerators
The SECDA-DSE framework introduces Large Language Models into the SECDA approach, facilitating the automation of design space exploration for FPGA-based accelerators tailored to AI tasks. This innovative system merges a structured DSE Explorer, which creates accelerator configurations, with an LLM Stack that employs retrieval-augmented reasoning to explore architectural parameters, dataflow methods, and memory hierarchies. As a result, it minimizes the manual labor and specialized knowledge usually necessary for pinpointing the best configurations.
Key facts
- SECDA-DSE integrates LLMs into the SECDA ecosystem
- Targets FPGA-based accelerators for AI workloads
- Combines DSE Explorer with LLM Stack
- Uses retrieval-augmented reasoning
- Automates navigation of architectural parameters, dataflow strategies, and memory hierarchies
- Reduces manual effort and need for domain expertise
- SECDA methodology enables rapid hardware-software co-design through SystemC simulation and FPGA execution
Entities
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