LLM-Based Framework for Analog Circuit Sizing with Interpretable Equations
A new system has been developed to automate analog circuit design, using a large language model (LLM) that generates specific analytical equations from basic circuit netlists. This model produces a detailed Python sizing function, linking each device's dimensions to a clear design rationale, which enhances interpretability compared to current approaches. It includes a deterministic calibration loop that gathers process-related parameters from a single DC operating point simulation, with a feedback system to correct any analytical mistakes. The framework has been successfully tested on circuits ranging from 8 to 30 transistors, including various designs like two-stage Miller-compensated and complementary class-AB outputs, across three different process nodes: 40 nm, 90 nm, and 180 nm. Benchmarks involved evaluations of the class-AB opamp against specified criteria.
Key facts
- Framework uses LLM to derive analytical equations from netlists.
- Each device dimension is traceable to a specific design rationale.
- Calibration loop extracts process-dependent parameters from a single DC simulation.
- Prediction-error feedback compensates for analytical inaccuracies.
- Validated on circuits with 8 to 30 transistors.
- Topologies include Miller-compensated, current-mirror, folded cascode, nested Miller-compensated, and class-AB output.
- Tested across 40 nm, 90 nm, and 180 nm process nodes.
- Benchmarks include matched-specification tests on class-AB opamp.
Entities
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