HYPERHEURIST Framework Uses Simulated Annealing to Optimize LLM-Generated Hardware Designs

A new simulated annealing-based control framework called HYPERHEURIST addresses limitations in Large Language Model-generated Register Transfer Level hardware designs. Traditional single-shot LLM approaches often fail to produce designs that are both functionally correct and power-efficient. The framework treats LLM-generated RTL as intermediate candidates rather than final outputs, implementing a two-phase optimization process. Initial RTL candidates undergo compilation, structural checks, and simulation to verify functional validity. Only designs passing these functional tests proceed to Power-Performance-Area optimization. Evaluations across eight RTL benchmarks demonstrate that this staged approach yields more stable and reliable results. The research focuses specifically on hardware design applications where both correctness and efficiency are critical. The framework represents arXiv preprint 2604.15642v1, categorized as a cross-announcement type. This methodology restricts PPA optimization exclusively to RTL designs that have successfully passed compilation and simulation stages.