Huawei proposes new chip scaling law to bypass ASML bottleneck
Huawei Technologies has introduced an innovative chip scaling method known as the Tau (τ) Scaling Law, designed to reduce dependence on advanced lithography machines from ASML, a Dutch supplier. Since 2019, the company has faced restrictions on accessing cutting-edge semiconductors, ASML's top-tier lithography tools, and electronic design automation (EDA) resources. This new approach focuses on compressing the effective time constant (τ) rather than merely reducing transistor sizes, thereby enhancing signal travel speed across devices and circuits. He Tingbo, chair of Huawei's Scientist Committee and head of its semiconductor division, stated that advancements in lithography tools are 'not necessary' with this strategy. However, analysts warn that substantial manufacturing hurdles persist, and the feasibility of this innovation remains uncertain. If it succeeds, it would represent a significant achievement for Huawei and China's pursuit of semiconductor self-sufficiency.
Key facts
- Huawei Technologies has proposed the Tau (τ) Scaling Law.
- The law aims to bypass the need for advanced lithography machines from ASML.
- Huawei has been cut off from advanced semiconductors, ASML lithography tools, and EDA software since 2019.
- The new approach focuses on 'time scaling' rather than shrinking transistors.
- He Tingbo stated that lithography improvements are 'not necessary' under this method.
- Analysts warn that manufacturing hurdles remain significant.
- The innovation is unproven and faces skepticism.
- Success would be a milestone for Huawei and China's semiconductor ambitions.
Entities
Institutions
- Huawei Technologies
- ASML
- Huawei Scientist Committee
Locations
- China
- Netherlands