HAVEN: LLM-Driven UVM Testbench Synthesis
The HAVEN (Hybrid Automated Verification ENgine) system tackles the challenges faced by LLMs in creating UVM testbenches for integrated circuit (IC) verification, which occupies about 70% of the development cycle. Due to the infrequency of Hardware Description Languages (HDLs) in training datasets, LLMs encounter difficulties. Rather than allowing LLMs to write HDL directly, HAVEN employs LLM agents to examine design specifications and formulate a detailed architectural outline. Subsequently, the HAVEN Template Engine integrates both predefined and protocol-specific templates to produce all UVM components, ensuring accurate bus-handshake timing.
Key facts
- IC verification consumes nearly 70% of the IC development cycle.
- LLMs have difficulty generating testbenches correctly due to rarity of HDLs in training data.
- HAVEN prevents LLMs from writing HDL directly.
- HAVEN uses LLM agents to analyze design specifications.
- HAVEN produces a structured architectural plan.
- HAVEN Template Engine combines predefined and protocol-specific templates.
- HAVEN generates all UVM components with correct bus-handshake timing.
- The system is proposed to overcome challenges in UVM testbench and sequence generation.
Entities
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