GAN-based method estimates fault tolerance in digital circuits
A new numerical method uses generative adversarial networks (GANs) to estimate fault tolerance in digital circuits. The approach compares ideal digital signals with realistic outputs from simulated circuit designs, identifying deviations caused by missing or interchanged logical devices. By representing the GAN in complex variables, the method differentiates the impact of failure modes across classical logical elements, enabling robustness evaluation in electronic designs.
Key facts
- Proposes a generative network sampling technique for fault tolerance estimation.
- Uses GAN discriminator to compare expected and realistic digital signals.
- Accounts for error modes like missing or interchanged logical devices.
- Represents GAN in terms of complex variables for analysis.
- Evaluates robustness by differentiating failure mode impacts.
- Method is numerical and applicable to digital circuit structures.
- Inputs are random bitwise configurations of digitalized analog currents.
- Focuses on classical logical gates in circuit design.
Entities
Institutions
- arXiv