AI Chip Placement: New Study Finds HPWL Poorly Predicts Timing

A recent study published on arXiv (2608.13790) questions the traditional reliance on half-perimeter wirelength (HPWL) as the main goal in chip macro placement. Findings indicate a minimal correlation between HPWL and post-route timing indicators, including worst negative slack (WNS) and total negative slack (TNS). In tests, all six artificial intelligence (AI) placers assessed performed worse in terms of power, performance, and area (PPA) compared to the hierarchical baseline. While recent initiatives have developed cross-stage predictors, they predominantly concentrate on macro-only models and utilize pre-route metrics for training. A label fidelity analysis of ten circuits across four design stages reveals that HPWL and pre-route timing inadequately represent final post-route timing rankings. Conversely, post-global-routing offers the optimal trade-off between timing accuracy and label generation efficiency. The paper introduces a differentiable cross-stage objective that utilizes post-global-routing features to enhance PPA, marking an important advancement for the AI and chip design sectors by revealing the shortcomings of current optimization metrics and proposing a more effective training method for AI placers.